(a) Field of the Invention
The present invention relates to thin film transistor (TFT) panel for a liquid crystal display (LCD) and a method for manufacturing the same.
(b) Description of the Related Art
An LCD is one of the most popular flat panel displays (FPD). The LCD has two panels having two kinds of electrodes for generating electric fields and a liquid crystal layer interposed there between. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
The field-generating electrodes may be formed at each of the panels, or at only one of the panels. A panel with at least one kind of electrode has switching elements, such as thin film transistors.
In general, a TFT array panel of an LCD includes a plurality of pixel electrodes and TFTs controlling the signals supplied to the pixel electrodes. The TFT array panel is manufactured by photolithography using a plurality of photomasks, and it undergoes five or six photolithography steps before it is completed. The high costs and lengthy time required for the photolithography process makes it desirable to reduce the number of the photolithography steps.
Several manufacturing methods of LCDs using only four photolithography steps have been suggested, such as that in Korean Patent Application No. 1995-189 (""189). However, as an LCD actually requires wires for transmitting electric signals to the TFTs and wire pads for receiving external signals, the full process to complete a TFT array panel requires the step of forming such pads. Unfortunately, ""189 does not disclose how to form such pads.
Another conventional method of manufacturing a TFT array panel using only four photolithography steps is disclosed in xe2x80x9cA TFT Manufactured by 4 Masks Process with New Photolithography (Chang-wook Han et al., Proceedings of The 18th International Display Research Conference Asia Display 98, pp. 1109-1112, 1998. 9.28-10.1).
Furthermore, a storage capacitor for sustaining the voltage applied to a pixel is generally provided in the TFT array panel, and the storage capacitor includes a storage electrode and a portion of a pixel electrode as well as a passivation layer interposed there between. The storage electrode is made of the same layer as a gate wire, and a portion of the pixel electrode is formed on the passivation layer. The storage electrode is covered with a gate insulating layer, a semiconductor layer, and a passivation layer, with most of the pixel electrode being formed directly on the substrate in Han et al. Therefore, the pixel electrode should be stepped up over the triple layers of the gate insulating layer, the semiconductor layer, and the passivation layer in order to overlap the storage electrode. This may result in a disconnection of the pixel electrode in the vicinity of a high step-up area.
As shown in ""189, conventional photolithography processes uses a photoresist (PR) layer. The conventional photoresist layer is exposed to light through a photomask and thereby divided into two sections, that is, the part exposed to the light and the other part that is not so exposed. The development of the photoresist layer forms the PR pattern having a uniform thickness once the PR layer exposed to the light has been completely removed. Accordingly, the etched thickness of the layers under the PR pattern is also uniform. However, Han et al. uses a photomask having a grid, which lowers the amount of light reaching the portion of a positive PR layer thereunder in order to form a PR pattern having some portions thinner than other portions. The different thicknesses of the PR pattern produces the different etching depths of the underlying layers.
However, the method of Han et al. has a problem in forming the grid throughout a wide region. Furthermore, it is hard to make the etching depth uniform under the grid region, even when the grid is formed throughout a wide region.
U.S. Pat. Nos. 4,231,811, 5,618,643, and 4,415,262 and Japanese patent publication No. 61-181130, etc., which disclose similar methods as do Han et al. also have the same problem.
It is therefore an object of the present invention to simplify the manufacturing method of a TFT array panel for an LCD, thereby reducing the manufacturing cost and increasing the productivity.
It is another object of the present invention to etch thin films to different uniform depths depending on position at the same time.
These and other objects are provided, according to the present invention, by forming a contact hole for a gate pad along with at least one other layer, or a data wire and a semiconductor pattern, using a photoresist pattern as the etch mask, which is formed by a single photolithography step, having different thickness depending on position.
At this time, the semiconductor pattern may be extended out from the data wire.
In the manufacturing method of a thin film transistor array panel for a liquid crystal display of the present invention, a gate wire including a plurality of gate lines, gate electrodes, and gate pads, and a common wire including common signal line and common electrodes, are formed on a substrate having a display area and a peripheral area. The gate lines, and the gate electrodes and the common wire are mainly located in the display area and the gate pads are mainly located in the peripheral area. A gate insulating layer pattern covering portions of the gate wire and the substrate in the display area and exposing at least a part of each gate pad is formed thereon. A semiconductor pattern is formed on the gate insulating layer pattern, and an ohmic contact layer pattern is formed on the semiconductor pattern. Then, a data wire including a plurality of data lines, source electrodes, and drain electrodes mainly located in the display area and a plurality of data pads mainly located in the peripheral area are formed on the ohmic contact layer pattern. Next, a passivation layer pattern is formed, and a pixel wire including a plurality of pixel electrodes and pixel signal lines and which are connected to the drain electrodes is formed. Here, the gate insulating layer pattern is formed along with the semiconductor pattern and the passivation layer pattern through a single photolithography process using a photoresist pattern having a thickness that varies depending on position.
Here, it is desirable that the photoresist pattern has a first portion located over the gate pads, a second portion that is thicker than the first portion and located in the display area, and a third portion that is thicker than the second portion.
The photoresist pattern is formed on the passivation layer. The gate insulating layer pattern, the semiconductor layer pattern, and the passivation layer pattern are formed by etching a passivation layer and a semiconductor layer under the first portion of the photoresist pattern, and the second portion of the photoresist pattern at the same time. Next, the second portion of the photoresist pattern, in order to expose the passivation layer thereunder, is removed by an ashing process, and the gate insulating layer and the passivation layer are etched by using the photoresist pattern as an etch mask to expose the gate pads under the first portion of the photoresist pattern and to expose the semiconductor layer under the second portion of the photoresist pattern. Next, a portion of the semiconductor layer under the second portion is removed by using the photoresist pattern as an etch mask.
The data pads may be exposed in the step of etching the portions of the passivation layer and the semiconductor layer, and the data pads are exposed in the step of etching the passivation layer and the gate insulating layer.
The drain electrodes may be exposed in the step of etching the passivation layer, or they may be exposed in the step of etching portions of the passivation layer and the semiconductor layer.
A plurality of redundant gate pads and redundant data pads respectively covering the gate pad and the data pad may be formed in the step of forming the pixel electrode.
The photoresist pattern may be formed by using a photomask having different transmittances. It is desirable that the transmittance of the photomask of the part corresponding to the second portion is 20% to 60% of that of the first portion and the transmittance of the part corresponding to the third portion is less than 3% of that of the first portion.
The photomask has a mask substrate and at least one mask layer, and the difference of transmittance between the first part and the second part is obtained by adjusting the mask layer materials of the first part and the second part, by differentiating the thickness of the mask layer, or by forming slits or a grid pattern smaller than the resolution of the stepper in the mask layer.
The data lines may be exposed in the step of etching the portions of the passivation layer, and a plurality of redundant data lines connected to the data line may be formed in the step of forming the pixel wire.
It is desirable that the photoresist layer is made of a positive photoresist.
In another method for manufacturing a thin film transistor array panel for a liquid crystal display in the present invention, a gate wire including a plurality of gate lines, gate electrodes connected to the gate line, and a common wire including a plurality of common electrodes are formed on an insulating substrate. A gate insulating layer pattern covering the gate wire and the common wire, a semiconductor pattern on the gate insulating layer, and an ohmic contact layer pattern on the semiconductor pattern are formed. A data wire is formed including a plurality of data lines, with source electrodes connected to the data lines, and drain electrodes separate from the source electrode on the ohmic contact layer pattern. A passivation layer pattern covering the data wire except for a part of the drain electrode is formed, and a plurality of pixel electrodes connected to the drain electrodes and generating electric fields with the common electrode is formed. Here, the pixel electrodes are located at different layer from the data wire. The source electrode and the drain electrode are separated by a photolithography process of using a photoresist layer pattern, which includes a first portion located between the source electrode and the drain electrode, a second portion thicker than the first portion, and a third portion thinner than the first portion.
It is desirable that a mask used for forming the photoresist pattern has a first, a second, and a third part, with the transmittance of the third part being higher than that of the first and the second parts, the transmittance of the first part being higher than that of the second part, and with the photoresist pattern being made of positive photoresist, and with the mask being aligned such that the first, the second, and the third parts respectively face the first, the second, and the third portions of the photoresist pattern in an exposing step.
Here, the first part partially may transmit light, the second part may be substantially opaque, and the third part may be substantially transparent.
At this time, it is desirable that the first parts of the mask include a partially transparent layer, and the first part of the mask include a pattern smaller than the resolution of the exposure device used in the exposing step.
The first portion may be formed by reflow.
It is desirable that the thickness of the first portion is less than half of the thickness of the second portion, the thickness of the second portion is 1 xcexcm to 2 xcexcm, and the thickness of the first portion is in the range of 2,000 xc3x85 to 5,000 xc3x85.
The data wire, the ohmic contact layer pattern, and the semiconductor pattern may be formed in the same photolithography process.
To form the gate insulating layer, the semiconductor pattern, the ohmic contact layer pattern, and the data wire, the gate insulating layer, a semiconductor layer, an ohmic contact layer, and a conductor layer are formed, and a photoresist layer is coated on the conductor layer. The photoresist layer is exposed to light through a mask and developed to form the photoresist pattern such that the second portion lies on the data wire due to the development the photoresist layer. The data wire, the ohmic contact layer pattern, and the semiconductor pattern respectively made of the conductor layer, the ohmic contact layer, and the semiconductor layer, are formed by etching a portion of the conductor layer under the third portion, the semiconductor layer and the ohmic contact layer thereunder, the first portion, the conductor layer and the ohmic contact layer under the first portion, and a partial thickness of the second portion, and removing the photoresist pattern.
To form the data wire, the ohmic contact layer pattern, and the semiconductor pattern, the portion of the conductor layer under the third portion is etched by dry or wet etching to expose the ohmic contact layer. The ohmic contact layer under the third portion, and the semiconductor layer thereunder, and the first portion are then etched to obtain the completed semiconductor pattern along with exposing the gate insulating layer under the third portion. Next, the first portion is removed to expose the conductor layer under the first portion, and the conductor layer under the first portion and the ohmic contact layer thereunder are removed to obtain the completed data wire and the completed ohmic contact layer pattern.
The first portion may be formed on the part corresponding to the edge portion of the data wire.
The passivation layer pattern has a first contact hole exposing the data line, and a redundant data line connected to the data line through the first contact hole on the passivation layer may be formed on the same layer as the pixel electrodes.
In a thin film transistor array panel for a liquid crystal display, a gate wire, a common wire, and a pixel wire are formed on the insulating substrate. The gate wire includes a plurality of gate lines extending in a first direction, and gate electrodes connected to the gate line, the common wire includes a plurality of common signal lines extending in the same direction as the gate line and a plurality of common electrodes connected to the common signal lines, and the pixel wire includes a plurality of pixel electrodes parallel to the common electrodes. A semiconductor layer made of semiconductor is formed on a gate insulating layer covering the gate wire, the common wire, and the pixel wire. Additionally, a data wire, including a plurality of data lines extending in a second direction crossing the gate line, source electrodes connected to the data lines, and drain electrode separated from the data line and the source electrode and located at the opposite side of the source electrode with respect to the gate electrode, is formed on the semiconductor layer. A passivation layer pattern having a first contact hole exposing the pixel wire and the drain electrode along with the gate insulating layer is formed on the data wire. A redundant conductive layer connecting the drain electrode to the pixel wire through the first contact hole is formed on the passivation layer pattern.
It is desirable that the conductive layer provides storage capacitance by overlapping the common wire, and with the conductive material made of transparent conductive material such as indium-tin-oxide or indium-zinc-oxide.
The passivation layer pattern may have a plurality of second contact holes exposing the data lines, and a redundant data line may be formed, which is made of the same layer as the redundant conductive layer and connected to the data line through the second contact holes.
An ohmic contact layer pattern is further included between the data wire and the semiconductor pattern and doped with impurity, the ohmic contact layer pattern having the same shape as the data wire.
The semiconductor pattern, except for the channel portion of a thin film transistor, may have the same shape as the data wire.
Here, the semiconductor pattern may be extended out from the data wire.
In another method for manufacturing a thin film transistor array panel for a liquid crystal display according to the present invention, a gate wire including a plurality of gate lines, gate electrodes connected to the gate line and a common wire including a plurality of common electrodes are formed on an insulating substrate. A gate insulating layer pattern that covers the gate wire and the common wire is formed, a semiconductor pattern is formed on the gate insulating layer, and an ohmic contact layer pattern is formed on the semiconductor pattern. A data wire including a plurality of data lines, source electrodes connected to the data line, and drain electrodes separate from the source electrode, is formed on the ohmic contact layer pattern. A passivation layer pattern covering the data wire, except for a part of the drain electrode, is formed, and a plurality of pixel electrodes connected to the drain electrodes and generating electric fields with the common electrodes are formed. At this time, the source electrode and the drain electrode are separated by a photolithography process using a photoresist layer pattern, which includes a first portion located between the source electrode and the drain electrode and least at the periphery portion of the pixel electrodes, a second portion thicker than the first portion, and a third portion thinner than the first portion.
It is desirable that the semiconductor pattern at least extends out from the pixel electrodes, and the photoresist pattern may have a double-layered structure made of a lower layer and an upper layer having different photosenstivity.
In another thin film transistor array panel for a liquid crystal display of the present invention, a gate wire and a common wire are formed on an insulating substrate. The gate wire includes a plurality of gate lines extending in a first direction and gate electrodes connected to the gate line, and the common wire includes a plurality of common signal lines extending to the same direction as the gate line and a plurality of common electrodes connected to the common signal lines. A gate insulating layer covering the gate wire and the common wire is formed, and a semiconductor layer is formed on the gate insulating layer and overlaps the gate electrode. A data wire and a pixel wire are formed on the semiconductor layer. The data wire includes a plurality of data lines extending in a second direction crossing the gate line, source electrodes connected to the data lines, and drain electrode separated from the data line and the source electrode and located at the opposite side of the source electrode with respect to the gate electrode, and the pixel wire that includes a plurality of pixel electrodes parallel to the common electrodes. At this time, at least the semiconductor pattern under the pixel electrodes is extended out from the pixel electrodes.
It is desirable that the width of the semiconductor pattern extended from out the pixel electrodes is more than 0.5 xcexcm.
The gate wire further includes a gate pad which is connected to and receives a scanning signal from an external circuit, and the data wire further includes a data pad which is connected to and receives a data signal from an external circuit. A passivation layer having contact holes respectively exposing the gate pad and the data pad along with the gate insulating layer may also be included.
The pixel wire further may include a pixel signal line connecting the pixel electrodes and the drain electrode and extending in the first direction.
In another thin film transistor array panel for a liquid crystal display of the present invention, a gate wire including a plurality of gate lines extending in a first direction, and gate electrodes connected to the gate line, and a common wire including a plurality of common signal lines extending in the same direction as the gate line and a plurality of common electrodes connected to the common signal lines are formed on an insulating substrate. A gate insulating layer covering the gate wire and the common wire is formed, and a semiconductor layer is formed on the gate insulating layer and made of semiconductor. A data wire including a plurality of data lines extending in a second direction crossing the gate line, source electrodes connected to the data lines, and drain electrode separated from the data line and the source electrode and located at the opposite side of the source electrode with respect to the gate electrode, is formed on the semiconductor layer. A passivation layer pattern having a first opening exposing the drain electrode is formed on the data wire. A pixel wire, including a plurality of pixel electrodes parallel to the common electrodes and a pixel signal line connecting the pixel electrodes and the drain electrode, is formed on the passivation layer.
It is desirable that the pixel wire provides storage capacitance by overlapping the common wire.
The passivation layer pattern may have a plurality of second contact holes exposing the data lines, and a redundant data line may also be formed, which are made of the same layer as the pixel wire and connected to the data line through the second contact holes.